This invention relates generally to the use of computers in the design of integrated circuits.
An essential step in designing very large scale integrated circuits is ensuring timing verification of all data signals flowing along timing paths within the integrated circuit. Timing verification involves making sure that data signals for all possible relevant paths within an integrated circuit arrive no later than a specified time and no earlier than another specified time with respect to one or more reference signals called clocks.
A common method for analyzing all of the relevant paths in an integrated circuit involves using industry available software called a static-timing tool. The tool identifies all possible timing paths coupled with designer specified irrelevant paths called false paths and other path exceptions such as multi-cycle paths. As a result, with the static-timing tool, irrelevant timing paths need not be analyzed for timing verification.
As integrated circuits increase in size and complexity, a block level strategy may be employed wherein the integrated circuit is divided into a plurality of blocks which may be functional blocks. However conventional static-timing verification techniques are not amenable to block level analysis. This is at least in part because current static-timing verification techniques do not permit the specification of the relevant timing paths at the boundaries of blocks.
Thus there is a need for a new approach to modeling integrated circuits as blocks for static-timing verification that allows exception paths such as irrelevant and multi-cycle paths to be specified at block boundaries.